ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

The IDDQ test relies on measuring the supply current (I DD) of an IC’s quiescent state, when the circuit isn’t switching and inputs are held at static values. Test patterns are used to place the ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

Design for Test (DFT) is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier ...