Semiconductor Engineering

Making Declarative Modeling Modular: Portable Stimulus Introduces Dynamic Constraints

Naturally, Accellera’s Portable Stimulus Standard (PSS) supports the powerful capabilities of advanced verification techniques that are well-known in the industry today, including object-oriented ...
EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
EDN

Who is the EDA leader in SystemVerilog simulation? Part 1

A couple of weeks ago, I took a pre-briefing from the folks at Mentor Graphics and Cadence Design Systems on their plans to standardize on a jointly developed common SystemVerilog verification ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...