Nasdaq

Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development

Arteris and Semidynamics partnership enhances the flexibility and highly configurable interoperability of RISC-V processor IP with system IP. Integrated and optimized solutions will focus on ...
Just Auto on MSN

Quintauris and eSOL team up on RISC-V automotive software integration

The partnership focuses on integrating eSOL’s “real-time” operating system technology with Quintauris’ RISC-V platforms.

DFRobot Showcases HUSKYLENS 2 at RISC-V Booth during embedded world 2026, Advancing AI Vision Education

From March 10 to 12, DFRobot is exhibiting at the RISC-V International booth (Hall 5, Booth 5-119) at embedded world 2026, presenting its latest HUSKYLENS 2 AI Vision Sensor. As a representative ...
Geeky Gadgets

RISC OS alternative operating system hits Kickstarter

A new Kickstarter project has launched this month, looking for backers to help build a power saving computer operating system and push RISC OS to more hardware platforms. German developer Stefan ...
Business Insider

Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification

SAN JOSE, Calif., Feb. 20, 2025 (GLOBE NEWSWIRE) -- Breker Verification Systems today confirmed its RISC-V SystemVIP library components and test suite synthesis product portfolio is deployed in more ...
TweakTown

RISC-V systems support replacing RAM sticks WITHOUT powering off the system

The upcoming version 6.11 of the mainline Linux kernel has support for RISC-V memory hot plugging, meaning you can pull RAM sticks out of your PC without turning it off... very nice. The Linux kernel ...
EDN

Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis

Developed with SiFive to address RISC-V system integration validation; generates high-impact SoC verification test suite with minimal manual effort. Breker Verification Systems, the leading provider ...
Semiconductor Engineering

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling

A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao ...
Semiconductor Engineering

Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.)

A new technical paper titled “Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems” was published by researchers at Inha University, Intel Labs, Electronics and ...
TechNode

China’s chip industry is embracing RISC-V

Every Wednesday and Friday, TechNode’s Briefing newsletter delivers a roundup of the most important news in China tech, straight to your inbox. Sign up On June 21, Nuclei System Technology, a Shanghai ...
Ars Technica

A history of ARM, part 1: Building the first chip

RISC is a somewhat misleading term, as a RISC processor doesn't *have* to have fewer instructions in its ISA than a CISC system (Though RISC architectures do tend to try to do so). For example, the ...