High-speed-digital serial I/O links and DDR memory interfaces are presenting significant measurement challenges as fourth-generation standards emerge. As signals travel at ever higher speeds over ...

In absence of any standards for serial flash memory, timing requirements are different for each vendor. Timing closure across PVT corners with shrinking technology nodes is a major challenge. Below, ...

I keep hearing about serial ATA and DDR II, but I really don't hear anyone giving much info about when we should really see these become common. This seems like a golden time for cheap processors, but ...

ARM, Denali, Intel, Rambus, Samsung, and Synopsys team on specification to address development challenges for DDR-DRAM memory systems PALO ALTO, Calif. -- Sept. 6, 2006 -- Denali Software, Inc., today ...

The rise of the cellular handset has revolutionized thinking on integrated systems architecture in many ways, from multiprocessing SOCs (systems on chip) to RF circuitry on CMOS logic chips. But the ...

The Open Coherent Accelerator Processor Interface (OpenCAPI), announced at this week's Flash Memory Summit, is managed by the OpenCAPI Consortium. It’s a new high-performance bus interface designed ...