Driven by the explosion of big data and expanding applications, chip design complexity is increasing. Applications such as high-performance computing (HPC), the Internet of Things (IoT), automotive, ...

The verification of analog and mixed-signal IPs can be challenging due to stringent design specifications and the steadily increasing complexity of system-on-chip (SoC) designs. That, in turn, calls ...

Design verification continues to consume the majority of engineering resources on today's ASIC and SOC design projects. Functional verification at the Register Transfer (RT) level, the process of ...

In the previous blog article, we took a look at some of the main power management verification issues encountered in low-power designs. Typical power management verification strategy requires a ...

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...

Claiming to be the industry's most advanced simulation acceleration and in-circuit emulation system, the Palladium combines a scalable simulation and emulation hardware architecture with an integrated ...

AMD’s Versal adaptive compute acceleration platform (ACAP) is a system-on-chip (SoC) device architecture (see figure 1) includes three groups of engines – scalar, adaptable, and intelligent – plus ...