Semiconductor Engineering

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...
EDN

A short course on SystemVerilog classes for UVM verification

Learning any language can be difficult when so many words take on different meanings in different contexts. “Why does a farmer produce produce?” These homonyms can be confusing even for native ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...
EDN

Getting in sync with UVM sequences

The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...
Semiconductor Engineering

Extending UVM To Analog

Analog/mixed-signal content in SoCs needs to be modeled in a similar way as the digital content but does UVM make sense for pure analog? Perhaps not. As SoC complexity has grown, so too has the need ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.