Design-Reuse

An Example Verification Environment for Different Types of Processor Models

Embedded systems are getting significant attention in current integrated circuits due to their direct control on the overall circuits` performance and functional capabilities. Commonly used processors ...
Semiconductor Engineering

Power-Aware Intent And Structural Verification Of Low-Power Designs

Cell-level and pin-level attributes from Liberty are mandatorily required for accurate PA-Static verification at the GL-netlist (post-synthesis) and PG-netlist (post P&R) levels of the design.
Design-Reuse

Unique Approach to Verification of Complex SoC Designs

AAI (Avnet ASIC Israel Ltd.) recently designed and implemented a group of SoC devices that connect several IPs from different vendors with customer specific IPs, around an industry standard AHB bus.
Semiconductor Engineering

Avoiding A $7.7B Chip Design Cost

For years, the story about semiconductor development cost and about EDA contributions has been pretty simple. Cost has been, is, and will likely be for a while, the single biggest issue in scaling ...